1. Field of the Invention
The present invention relates to a manufacturing process for a chip package structure. More particularly, the present invention relates to a manufacturing process for a Quad Flat Non-leaded (QFN) chip package structure.
2. Description of Related Art
The semiconductor industries have bee highly developed. With the trends of electrification, electronic and semiconductor devices are widely used in the daily life, including entertainment, education, transportation and households. The design of the electrical products becomes more complex, smaller-sized, light-weight and humanized, in order to offer more convenience for the consumers. In the package structures, the leadframe is one of the most commonly used elements, applied in various package products. Based on the type of leadframes, the Quad Flat Packages (QFP) can be categorized as quad flat chip package with “I” lead (QFI), quad flat chip package with “J” lead (QFJ) and Quad Flat Non-leaded (QFN) chip package. Because leads of the leadframe in the QFN chip package end at the edges of the chip package structure, the QFN chip package has a small size. Since the QFN chip package provides shorter electrical path and faster signal transmission, the QFN chip package has been widely used as low pin count solutions for power elements.
In general, in the fabricating process of a QFN chip package, a plurality of chips are disposed on the leadframe, wherein the leadframe includes a plurality of lead sets connected to each other and each chip is surrounded by one lead set. Each chip is electrically connected to one lead set through wire bonding. Then, at least one molding compound is formed to encapsulate the leadframe, the chips and the bonding wires. Finally, a plurality of QFN chip packages are formed through a singulation process, wherein the sigulation process includes a punch process or a sawing process.